Job Responsibilities:

Collaborate with architecture engineers to develop micro-architectures;

Develop RTL for modules;

Work with the verification team to formulate verification plans, conduct functional debugging, analyze and improve verification coverage until verification convergence is achieved;

Collaborate with the backend team to complete PPA optimization;

Qualifications:

Prior experience in miner ASIC is preferred;

Familiar with micro-architecture design, RTL Coding, synthesis, and related processes;

Proficient in Verilog, SystemVerilog, and have a solid understanding of logic design knowledge;

Experience with tape-outs and familiarity with the toolchain requirements and workflow is preferred;

Excellent fresh graduates will be considered.

Base HongKong/Shenzhen

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