Job Responsibilities:

Collaborate with frontend designers to optimize chip area, power consumption, timing analysis, and layout planning.

Responsible for the physical implementation of digital chips, including synthesis and floorplanning, from netlist to GDS.

Coordinate with the frontend design department to optimize design performance and power consumption.

Responsible for the design and implementation of PV, PI, ESD, DFM, package selection, and other related aspects.

Responsible for chip timing analysis and timing closure.

Job Requirements:

Bachelor's degree or above in Microelectronics, Integrated Circuits, or related fields. Priority will be given to candidates with experience in backend design and backend processes.

Proficient in using frontend EDA tools and processes such as DC, PT, Innovus, ICC2, Formality, Spyglass, ICC/ICC2/Innovus, PT, Star-RC, Calibre, etc.

Familiar with SDC and STA, as well as ECO and low-power processes.

Familiar with hardware description languages such as Verilog, and proficient in Makefile, Perl, shell, and Python.

A strong sense of responsibility and ability to deliver tasks on time.

Base HongKong/Shenzhen

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