Responsibilities

Dealing with block level DFT design which includes Scan/MBIST/IP test in a large-scale chip.

Design synthesis & assist Physical Design team for DFT timing closure.

Responsible for DFT verification and simulation.

Responsible for ATE pattern generation.

Support test team for test program debugging.

Qualifications

Bachelor degree and above in Electrical & Electronic Engineering, Computer Science or equivalent

Knowledge of DFT principles.

Experience with Scan/ijtag/MBIST circuit structures and principles.

Experience with VCS or Verdi.

Knowledge of STA.

Knowledge of ATE in a plus.

Able to improve work efficiency by automation using scripting languages, such as Python and Perl is a plus.

Strong problem solving skills.

Base HongKong/Shenzhen

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